Field of the Invention
The present invention relates to a decode switch. More particularly, the present invention relates to a method for controlling a decode switch.
Description of the Related Art
FIG. 1 is a schematic diagram showing a conventional decode switch 100. The decode switch 100 includes a power source 110 and n decode paths 121-12n coupled to the power source 110. n is a preset integer larger than one. Each decode path includes two switches, a capacitance, and an output terminal. For example, the decode path 121 includes two switches ENA and DISA, a capacitance CL1, and an output terminal OUTA. The decode path 122 includes two switches ENB and DISB, a capacitance CL2, and an output terminal OUTB, and so on.
The power source 110 provides the preset voltage VPP. By controlling the switches ENA-ENn and DISA-DISn, the power source 110 can charge one or more capacitances CL1-CLn of one or more decode paths 121-12n from the reference voltage VBS (the reference voltage VBS may be a ground voltage or a deselect voltage) to the preset voltage VPP. The charging of the capacitances CL1-CLn raises the voltage of the output terminals OUTA-OUTn from the VBS to the preset voltage VPP. The raising of the voltage of an output terminal is also known as asserting the output terminal.
The decode switch 100 can be used in many circuit systems, such as in address decoders of memories.
FIG. 2 is a schematic diagram showing a conventional method for controlling the decode switch 100 to switch the assertion from the output terminal OUTA to the output terminal OUTB. At the time moment T1, the switch ENA is turned on and the switch DISA is turned off, thus connecting the capacitance CL1 to the power source 110 through the switch ENA. The power source 110 asserts the output terminal OUTA by charging the capacitance CL1 of the decode path 121.
At the time moment T2, the switches DISA and ENB are turned on, while the switches ENA and DISB are turned off. The capacitance CL1 is disconnected from the power source 110 and is connected to the reference voltage VBS through the switch DISA. Consequently, the capacitance CL1 begins discharging to the VBS. At the same moment T2, the capacitance CL2 is connected to the power source 110 through the switch ENB. At the time moment T3, the power source 110 asserts the output terminal OUTB by charging the capacitance CL2 of the decode path 122. The time period Tso between the moments T2 and T3 is the setup time of the output terminal OUTB of the decode path 122.
At the time moment T4, the switch ENB is turned off and the switch DISB is turned on. The capacitance CL2 is disconnected from the power source 110 and is connected to the ground through the switch DISB. Consequently, the capacitance CL2 begins discharging to the VBS. The electric charges previously stored in the capacitances CL1 and CL2 are simply squandered to the reference voltage VBS (a ground or a deselect voltage).
FIG. 3 is a schematic diagram showing a conventional method for controlling the decode switch 100 to assert all of the output terminals OUTA-OUTn. In FIG. 3, EN_all represents the switches ENA-ENn, DIS_all represents the switches DISA-DISn and OUT_all represents all of the output terminals OUTA-OUTn. At the time moment T1, the switches ENA-ENn are turned on and the switches DISA-DISn are turned off, thus connecting all of the capacitances CL1-CLn to the power source 110. The power source 110 asserts the output terminals OUTA-OUTn by charging the capacitances CL1-CLn of the decode paths 121-12n. The setup speed of the decode paths is slow because the power source 110 needs to charge all of the capacitances CL1-CLn.